Floating gate transistor is widely adopted in NVM devices like Flash, EPROM (Electrically Programmable Read-Only-Memory) and EEPROM (Electrically Erasable Programmable Read-Only Memory) because of its capability to store charges after power down. When a floating gate transistor is adopted in a memory cell, different voltages are needed during different operations. For example, two voltages are needed during erase operation, and the voltage difference between the two voltages may reach three times the power supply voltage. In a prior art voltage control circuit for providing voltages to the floating gate transistor, the highest voltage which is three times the power supply voltage together with a ground reference are provided during the erase operation. As a result, a high voltage circuit process is required to implement the voltage control circuit, which highly increases the cost.
Therefore, there is a need to provide a voltage control circuit implemented with low voltage circuit process to provide required voltages during different operations to the floating gate transistor.